MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 33

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Section Number
Freescale Semiconductor, Inc.
14.7
14.8
DDR PHY...................................................................................................................................................................1095
Programmable Registers.............................................................................................................................................1106
14.6.2
14.7.1
14.7.2
14.7.3
14.7.4
14.7.5
14.7.6
14.7.7
14.7.8
14.7.9
14.7.10
14.8.1
14.8.2
14.8.3
14.8.4
14.8.5
14.8.6
14.8.7
14.8.8
14.8.9
14.8.10
14.8.11
14.8.12
14.8.13
Command Execution Order After Placement..........................................................................................1093
High Level Block Diagram......................................................................................................................1095
DFI...........................................................................................................................................................1096
I/O Timing of Address and Command.....................................................................................................1096
Data Slice Overview................................................................................................................................1098
Read Data Capture...................................................................................................................................1099
Synchronize Read Data From delayed_dqs to emi_clk Domain.............................................................1099
Write Data Path.......................................................................................................................................1101
Write Data Path Low-Latency Option ....................................................................................................1102
Digital DLL and the Delay-Line.............................................................................................................1102
Configure output enable of I/O Control..................................................................................................1105
DRAM Control Register 00 (HW_DRAMCTL00).................................................................................1111
AXI Monitor Control (HW_DRAMCTL01)...........................................................................................1112
DRAM Control Register 02 (HW_DRAMCTL02).................................................................................1113
DRAM Control Register 03 (HW_DRAMCTL03).................................................................................1114
DRAM Control Register 04 (HW_DRAMCTL04).................................................................................1114
DRAM Control Register 05 (HW_DRAMCTL05).................................................................................1115
DRAM Control Register 06 (HW_DRAMCTL06).................................................................................1115
DRAM Control Register 07 (HW_DRAMCTL07).................................................................................1115
DRAM Control Register 08 (HW_DRAMCTL08).................................................................................1116
DRAM Control Register 09 (HW_DRAMCTL09).................................................................................1117
AXI0 Debug 0 (HW_DRAMCTL10)......................................................................................................1118
AXI0 Debug 1 (HW_DRAMCTL11)......................................................................................................1118
AXI1 Debug 0 (HW_DRAMCTL12)......................................................................................................1119
14.6.1.6
14.6.2.1
14.6.2.2
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Read/Write Grouping............................................................................................................1093
Command Aging...................................................................................................................1093
High-Priority Command Swapping.......................................................................................1094
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