MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1008

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
enabled. When one or more of the channels is enabled, the controller fetches the control
packet pointed to by that channel and initiates data fetches from the source buffer. Data is
then processed as described in the control packet and stored back to the system memory.
Once the processing for a control packet is complete, the controller writes completion status
information back to the control packet, and optionally stores relevant state information to
the context buffer. If the control packet specifies a subsequent control packet, the channel's
pointer is updated to the address for the next packet and an optional interrupt can be issued
to the processor.
At this point, the DCP module arbitrates among the virtual channels for the next operation
and processes its control packet. If a subsequent operation is continued from a previous
operation, the controller automatically loads the context from the previous session into the
working registers before resuming operation for that channel.
13.2.6.1 Virtual Channels
The DCP module processes data through work packets stored in memory. Each of the
channels contains a pointer to the current work packet and enough control logic to determine
whether the channel is active and to provide status to the processor. Each channel also
provides a recovery timer to help throttle processing by a particular channel. After processing
a packet, the channel enables its 16-bit recovery timer (if the recovery time is set to a
non-zero value). The channel will not become active again until its recovery timer has
expired. The recovery timer timebase is 16 HCLK cycles, so the timer acts as a 20-bit timer
with the bottom four bits implicitly tied to 0. This provides an effective range of zero to
220-1 clocks or 0 ns to 7.8 ms at 133 MHz.
A channel is activated any time its semaphore is non-zero and its recovery timer is cleared.
The semaphore can be incremented by software to indicate that the chain pointer has been
loaded with a valid pointer. As the hardware completes the work packets, it decrements the
semaphore if the Decrement Semaphore flag in the Control 0 field is set. Work packets may
be chained together using the CHAIN or CHAIN_CONTIGUOUS bits in the Control0 field,
which causes the channel to automatically update the work packet pointer to the value in
the NEXT_COMMAND_ADDRESS field at the end of the current work packet.
13.2.6.2 Context Switching
The control logic maintains four virtual channels that allow the DCP block to time-multiplex
encryption, hashing and memcopy operations, it must also retain state information when
changing channels so that when a channel is resumed, it can resume the operation from
where it left off. This process is called context-switching.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1008
Freescale Semiconductor, Inc.