MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 119
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MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
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Freescale Semiconductor, Inc.
• One fixed PTE at location 2048 covers the i.MX28 PIO and register space. The location
• Each MPTE requires a location register, such that it can be mapped to any of the 4K
• Each HW_DIGCTL_MPTEn_LOC must be programmed with a 12-bit value that
• The spanning feature can be enabled by adjusting the value of
is fixed as virtual = real, is non-cacheable, and includes programmable bufferable,
domain, and AP fields.
L1 section descriptors. In addition, each of these location registers can be programmed
to be bound to up to 128 locations each (covering up to 128 MB of physical each).
These location registers (HW_DIGCTL_MPTEn where n = 0...15) are located in the
DIGCTL module. Refer to
corresponds to one of the 4K section entries. Once programmed, the AHB physical
address of the MPTE is determined as:
HW_DIGCTL_MPTEn_SPAN. This is a 3-bit value which determines the size of the
span as 2^SPAN. This means that any access to the L1PT within the span will have the
following properties:
• The reset state of each HW_DIGCTL_MPTEn_LOC register is n (n = 0...15), for
• None of the MPTEn_LOC registers should be programmed to 0x800 (2048). This
• No checking/status is given for incorrect programming (for example, overlap). If
• The span allows any MPTE to bind to a range of MPTEn_LOC * 4 through to
• Because spanning binds a single MPTE to multiple L1PT entries, the DFLPT must
0x800C_0000 + (HW_DIGCTL_MPTEn_LOC << 2)
HW_DIGCTL_MPTEn_LOC = 0x000 – 0xFFF
example, HW_DIGCTL_MPTE3_LOC has reset value of 0x0000_0003.
corresponds to the fixed entry that covers the i.MX28 register space.
multiple MPTEs are programmed to the same address in the DFLPT, the behavior
is non-deterministic. The only exception is that all but one of the entries has DIS=1
set (disabled).
(MPTEn_LOC + (2^SPAN – 1) ) * 4, where SPAN is an integer from 0 to 7.
generate unique base addresses for each spanned entry, otherwise each 1 MB section
would map to the same physical section. The DFLPT achieves this by assuming
contiguous 1 MB section addressing for all sections covered within a span.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
MPTE0_LOC
for a description of the MPTEn_LOC registers.
Chapter 3 Default First-level Page Table (DFLPT)
119
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