MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1761

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

27.5.6 I2C Status Register (HW_I2C_STAT)
The I2C Controller reports status information in the I2C Status Register.
The status register provides read-only access to the function presence bits, as well as the
busy indicators for the slave and master state machines.
EXAMPLE
while(HW_I2C_STAT.SLAVE_BUSY != BV_I2C_STAT_SLAVE_BUSY__IDLE_VAL);// then wait till it finishes
Freescale Semiconductor, Inc.
MASTER_LOSS_
EARLY_TERM_
SLAVE_STOP_
XFER_TERM_
OVERSIZE_
SLAVE_IRQ
Field
IRQ
IRQ
IRQ
IRQ
4
3
2
1
0
This bit is set to indicate that an interrupt is requested by the I2C controller. This bit is cleared by software
by writing a one to its SCT clear address. This interrupt indicates that a master DMA transfer did not complete
by the end of the transfer size. This is indicated by the slave acknowledging the last byte of a write transfer
instead of NAKing it. The master should then send additional bytes of data if desired. This interrupt is only
used in slave mode.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the I2C controller. This bit is cleared by software
by writing a one to its SCT clear address. This interrupt indicates that a master write transfrom from the
STMP38xx to a slave device was NAKed by the slave before the transfer was completed. In slave mode, it
indicates that the master NAKed a byte transmitted by the slave causing early termination of the expected
transfer.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the I2C controller. This bit is cleared by software
by writing a one to its SCT clear address. This interrupt indicates that a master read or write transaction lost
an arbitration with another master. Master loss is indicated by the master attempting to transmit a one to
the bus at the same time as another master writes a zero. The wired and bus produces a zero on the bus
which is detected by the lossing master.
0x0
0x1
This bit is set to indicate that an I2C Stop Condition was received by the slave address search engine after
it had found a start command addressed to its slave address.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the I2C controller. This bit is cleared by software
by writing a one to its SCT clear address. This bit is set by the slave search engine to indicate that it has
stopped searching due to an address match or error.
0x0
0x1
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_I2C_CTRL1 field descriptions (continued)
Description
Chapter 27 Inter IC (I2C)
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