MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1430

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
20.4.1 OTP Controller Control Register (HW_OCOTP_CTRL)
The OCOTP Control and Status Register specifies the copy state, as well as the control
required for random access of the OTP memory
HW_OCOTP_CTRL: 0x000
HW_OCOTP_CTRL_SET: 0x004
HW_OCOTP_CTRL_CLR: 0x008
HW_OCOTP_CTRL_TOG: 0x00C
The OCOTP Control and Status Register provides the necessary software interface for
performing read and write operations to the On-Chip OTP (One-Time Programmable ROM).
The control fields such as WR_UNLOCK, ADDR and BUSY/ERROR may be used in
conjunction with the HW_OCOTP_DATA register to perform write operations. Read
operations are performed through the direct memory mapped registers. In the cases where
OTP values are shadowed into local memory storage, the memory mapped location can be
read directly. In the cases where the OTP values are not shadowed into local memory, the
read-preparation sequence involving RD_BANK_OPEN and BUSY/ERROR fields must
be used before performing the read.
Address:
1430
Reset
8002_C2A0
8002_C260
8002_C270
8002_C280
8002_C290
Absolute
address
Bit
W
(hex)
R
31
0
HW_OCOTP_CTRL
Shadow Register for OTP Bank4 Word4 (Data Use 4)
(HW_OCOTP_SRK4)
Shadow Register for OTP Bank4 Word5 (Data Use 5)
(HW_OCOTP_SRK5)
Shadow Register for OTP Bank4 Word6 (Data Use 6)
(HW_OCOTP_SRK6)
Shadow Register for OTP Bank4 Word7 (Data Use 7)
(HW_OCOTP_SRK7)
OTP Controller Version Register (HW_OCOTP_VERSION)
30
0
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
0
HW_OCOTP memory map (continued)
8002_C000h base + 0h offset = 8002_C000h
Register name
27
0
26
0
25
0
WR_UNLOCK
24
0
23
0
22
0
(in bits)
Width
32
32
32
32
32
21
0
Access
R/W
R/W
R/W
R/W
R
20
0
Freescale Semiconductor, Inc.
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0105_0000h
19
0
18
0
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20.4.43/1461
17
0
Section/
page
16
0