MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1248

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Programmable Registers
15.4.2 GPMI Compare Register (HW_GPMI_COMPARE)
The GPMI compare register specifies the expect data and the xor mask for comparing to
the status values read from the device. This register is used by the Read and Compare
command.
Address:
Re-
15.4.3 GPMI Integrated ECC Control Register (HW_GPMI_ECCCTRL)
HW_GPMI_ECCCTRL: 0x020
HW_GPMI_ECCCTRL_SET: 0x024
1248
set
Bit
W
R
XFER_COUNT
REFERENCE
INCREMENT
ADDRESS_
ADDRESS
31
0
22 20
19 17
31 16
MASK
Field
15 0
Field
15 0
CS
16
30
0
29
0
HW_GPMI_COMPARE
28
0
Selects which chip select is active for this command.
In NAND mode, use A0 for CLE and A1 for ALE.
0x0
0x1
0x2
0= Address does not increment.
1= Increment address.
In NAND mode, the address will increment once, after the first cycle (going from CLE to ALE).
0x0
0x1
Number of words (8 bit wide) to transfer for this command. A value of zero will transfer 64K words.
16-bit mask which is applied after the read data is XORed with the REFERENCE bit field.
16-bit value which is XORed with data read from the NAND device.
27
0
26
0
NAND_DATA — In NAND mode, this address is used to read and write data bytes.
NAND_CLE — In NAND mode, this address is used to write command bytes.
NAND_ALE — In NAND mode, this address is used to write address bytes.
DISABLED — Address does not increment.
ENABLED — Increment address.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_GPMI_CTRL0 field descriptions (continued)
MASK
24
0
HW_GPMI_COMPARE field descriptions
23
0
22
0
8000_C000h base + 10h offset = 8000_C010h
21
0
20
0
19
0
18
0
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
REFERENCE
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0

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