MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1293
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
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16.6.4 Hardware BCH ECC Loopback Encode Buffer Register
When performing memory to memory operations, indicates the address of the encode buffer.
This register should be programmed before writing a 1 to the M2M_ENABLE bit in the
CTRL register.
For memory to memory operations, this register is used as the pointer to the encoded data,
which is an output when encoding and an input while decoding.
EXAMPLE
Address:
Re-
16.6.5 Hardware BCH ECC Loopback Data Buffer Register
When performing memory to memory operations, indicates the address of the data buffer.
For memory to memory operations, this register is used as the pointer to the data to encode
or the destination buffer for decode operations.
EXAMPLE
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
31
31
0
0
ADDR
Field
31 0
30
30
0
0
29
29
0
0
(HW_BCH_ENCODEPTR)
(HW_BCH_DATAPTR)
HW_BCH_ENCODEPTR
HW_BCH_DATAPTR
28
28
0
0
Address pointer to encode buffer. This is the source for decode operations and the destination for encode
operations. This value must be aligned on a 4 byte boundary.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
HW_BCH_ENCODEPTR field descriptions
23
23
0
0
8000_A000h base + 40h offset = 8000_A040h
22
22
0
0
8000_A000h base + 30h offset = 8000_A030h
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
ADDR
ADDR
16
16
0
0
15
15
0
0
Description
Chapter 16 20-BIT Correcting ECC Accelerator (BCH)
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
1293
0
0
0
0
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