MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 808

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
HW_PINCTRL_DIN4_CLR: 0x948
HW_PINCTRL_DIN4_TOG: 0x94C
This register reflects the current values of all the bank 4 pins. The register accurately reflects
the state of the pin regardless of the setting of the HW_PINCTRL_MUXSELx or
HW_PINCTRL_DOEx registers, but generally, if it is desired to use a pin as a general
purpose input, the pin's two bits in the HW_PINCTRL_MUXSELx register should be set
to 3 (GPIO mode) and the pin's bit in the HW_PINCTRL_DOEx register should be set to
0 (disabled) to insure that the chip is not driving the pin.
Address:
Re-
9.4.53 PINCTRL Bank 0 Data Output Enable Register
The PINCTRL Bank 0 Output Enable Register controls the output enable signal for all pins
in bank 0 that are configured for GPIO mode.
HW_PINCTRL_DOE0: 0xb00
HW_PINCTRL_DOE0_SET: 0xb04
HW_PINCTRL_DOE0_CLR: 0xb08
HW_PINCTRL_DOE0_TOG: 0xb0C
For pins in bank 0 that are configured as GPIOs, a 1 in this register will enable the
corresponding bit value from HW_PINCTRL_DOUTxx register to be driven out the pin,
and a 0 in this register will disable the corresponding driver.
808
set
Bit
W
R
31
RSRVD1
0
31 21
Field
20 0
DIN
30
0
29
0
(HW_PINCTRL_DOE0)
HW_PINCTRL_DIN4
28
0
Empty Description.
Each bit in this read-only register corresponds to one of the 21 pins in bank 4. The current state of each pin
in bank 4, synchronized to HCLK, may be read here.
27
RSRVD1
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
HW_PINCTRL_DIN4 field descriptions
8001_8000h base + 940h offset = 8001_8940h
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
Description
14
0
13
0
12
0
11
0
DIN
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0