MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1853

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

29.9.9 ENET SWI Defines several global configuration settings.
Defines several global configuration settings.
Address:
Freescale Semiconductor, Inc.
Reset
Reset
TRANSPARENT
P0BUF_CUT_
STATSRESET
THROUGH
Bit
Bit
W
W
RSRVD1
R
R
30 10
CRC_
Field
31
9
8
31
15
0
0
(HW_ENET_SWI_MODE_CONFIG)
HW_ENET_SWI_MODE_CONFIG 800F_8000h base + 24h offset = 800F_
8024h
30
14
0
0
Reset Statistics Counters Command.
When set during a write, all statistics counters are cleared.
When set, all other bits are ignored and do not influence the currently stored value in the register (i.e. it is
not necessary to read/preserve the register contents prior to writing this bit).
Reserved bits. Write as 0.
Enable Port0 input buffer cut-through mode. Cut-through mode may be used for allowing jumbo frames to
be transferred.
When cleared (0, default) the input buffer operates in store/forward mode, which is the recommended mode
of operation.
When enabled (1) the MAC ports are expected to process frames to/from the switch including CRC. Frames
from a MAC port to a MAC port will then have their respective ff_rx_crc_fwd1/2 pin (wired to MAC's
ff_tx_crc_fwd) asserted, indicating that no CRC should be appended.
However, even when enabled, the DMA0 port is not expected to provide frames with crc: Frames from port
0 (DMA0 transmit) are always forwarded with the crc option as defined by the input ff_tx_crc_fwd0,
independent of the crc_transparent setting. This means, if the DMA0 port will never transmit frames with
CRC, ff_tx_crc_fwd0 can be wired to permanently 0.
Note that the MAC configuration bit RCR(CRC_FWD) must be set to ensure the MAC forwards received
frames with CRC to the switch.
RSRVD1[15:10]
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_ENET_SWI_MODE_CONFIG field descriptions
28
12
0
0
27
11
0
0
26
10
0
0
Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH)
25
0
0
9
24
0
0
RSRVD1[30:16]
8
Description
23
0
0
7
22
0
0
6
21
0
5
0
RSRVD0
20
0
4
0
19
0
0
3
18
0
0
2
17
0
0
1
1853
16
0
0
0