MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2276

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
2276
THRESHOLD1_
THRESHOLD0_
LRADC3_IRQ_
LRADC2_IRQ_
LRADC1_IRQ_
LRADC0_IRQ_
DETECT_IRQ
DETECT_IRQ
DETECT_IRQ
DETECT_IRQ
DETECT_IRQ
LRADC7_IRQ
BUTTON1_
BUTTON0_
RSRVD1
TOUCH_
15 13
Field
EN
EN
EN
EN
19
18
17
16
12
11
10
9
8
7
Set to one to enable an interrupt for channel 3 conversions.
0x0
0x1
Set to one to enable an interrupt for channel 2 conversions.
0x0
0x1
Set to one to enable an interrupt for channel 1 conversions.
0x0
0x1
Set to one to enable an interrupt for channel 0 conversions.
0x0
0x1
Reserved
This bit is set to one upon detection of the button1 condition in button matrix and attached to LRADC1. It is
ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion
hardware, this bit remains set until cleared by software.
0x0
0x1
This bit is set to one upon detection of the threshold1 condition in button matrix and attached to LRADC0.
It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion
hardware, this bit remains set until cleared by software.
0x0
0x1
This bit is set to one upon detection of the threshold1 condition. It is ANDed with its corresponding interrupt
enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared
by software.
0x0
0x1
This bit is set to one upon detection of the threshold0 condition. It is ANDed with its corresponding interrupt
enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared
by software.
0x0
0x1
This bit is set to one upon detection of a touch condition in the touch panel attached to LRADC2-LRADC6.
It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion
hardware, this bit remains set until cleared by software.
0x0
0x1
This bit is set to one upon completion of a scheduled conversion for channel 7(BATT). It is ANDed with its
corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit
remains set until cleared by software.
DISABLE — Disable Interrupt request.
ENABLE — Enable Interrupt request.
DISABLE — Disable Interrupt request.
ENABLE — Enable Interrupt request.
DISABLE — Disable Interrupt request.
ENABLE — Enable Interrupt request.
DISABLE — Disable Interrupt request.
ENABLE — Enable Interrupt request.
CLEAR — Interrupt request cleared.
PENDING — Interrupt request pending.
CLEAR — Interrupt request cleared.
PENDING — Interrupt request pending.
CLEAR — Interrupt request cleared.
PENDING — Interrupt request pending.
CLEAR — Interrupt request cleared.
PENDING — Interrupt request pending.
CLEAR — Interrupt request cleared.
PENDING — Interrupt request pending.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_LRADC_CTRL1 field descriptions (continued)
Description
Freescale Semiconductor, Inc.