MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2083

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
DOTCLK_MODE
READ_WRITEB
VSYNC_MODE
VSYNC_EDGE
DATA_SELECT
DATA_SHIFT_
INPUT_DATA_
SHIFT_NUM_
YCBCR422_
WAIT_FOR_
DVI_MODE
CLKGATE
BYPASS_
SWIZZLE
SFTRST
COUNT
INPUT
25 21
15 14
BITS
Field
DIR
31
30
29
28
27
26
20
19
18
17
16
This bit must be set to zero to enable normal operation of the LCDIF. When set to one, it forces a block level
reset.
This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block.
Zero implies input data is in RGB color space. One implies input data is in YCbCr 4:2:2 format, such that
YCbYCr are packed in a 32-bit word. It also means that there are 2 pixels in 4 bytes. If this bit is set, software
should program the H_COUNT field in the TRANSFER_COUNT register to the total number of pixels that
will have to be fetched by the LCDIF block per line and the BYTE_PACKING_FORMAT should be 0xF. The
WORD_LENGTH does not matter in this case.
By default, LCDIF is in the write mode. Setting this bit to 1 will make the hardware go into 6800/8080 system
read mode. Make sure that DMA operation is selected (LCDIF_MASTER bit is 0) when performing read
operations.
Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers
to the LCD. Used only in the VSYNC mode of operation.
Use this bit to determine the direction of shift of transmit data. In the DVI mode, it works only on the active
data, not on the timing codes and ancillary data.
0x0
0x1
The data to be transmitted is shifted left or right by this number of bits.
Set this bit to 1 to get into theITU-R BT.656 digital video interface mode. Toggle this bit from 1 to 0 to make
the hardware go out of DVI mode after completing all data transfer, deasserting the RUN bit and toggling
the dma_end_cmd signal.
When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount
of data indicated by the HW_LCDIF_TRANSFER_COUNT register has been transferred out. When this bit
is set to 1, the block will continue normal operation indefinitely until it is told to stop. This bit must be 0 in
system and VSYNC modes, and must be 1 in DOTCLK and DVI modes of operation.
Setting this bit to 1 will make the LCDIF hardware go into VSYNC mode. WAIT_FOR_VSYNC_EDGE can
be used only if this bit is set. If VSYNC signal is required to be an output from the block, SYNC_SIGNALS_ON
bit in HW_LCDIF_VDCTRL4 register must be set.
Set this bit to 1 to make the hardware go into the DOTCLK mode, i.e. VSYNC/HSYNC/DOTCLK/ENABLE
interface mode. ENABLE is optional, selected by the ENABLE_PRESENT bit. Toggle this bit from 1 to 0 to
make the hardware go out of DOTCLK mode after completing all data transfer and deasserting the RUN bit.
Command Mode polarity bit. This bit should only be changed when RUN is 0.
0x0
0x1
This field specifies how to swap the bytes either in the HW_LCDIF_DATA register or those fetched by the
AXI master part of LCDIF.The swizzle function is independent of the WORD_LENGTH bit. See the explanation
of the HW_LCDIF_DATA below for names and definitions of data register fields. The supported swizzle
configurations are:
0x0
TXDATA_SHIFT_LEFT — Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
TXDATA_SHIFT_RIGHT — Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
CMD_MODE — Command Mode. DCn signal is Low.
DATA_MODE — Data Mode. DCn signal is High.
NO_SWAP — No byte swapping.(Little endian)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_LCDIF_CTRL field descriptions
Description
Chapter 33 LCD Interface (LCDIF)
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