MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1269

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

16.4 Programming the BCH/GPMI Interfaces
Programming the BCH for NAND operations consists largely of disabling the soft reset
and clock bits (SFTRST and CLKGATE) from the HW_BCH_CTRL register and then
programming the flash layout registers to correspond to the format of the attached NAND
device(s). The HW_BCH_LAYOUTSELECT register should also be programmed to map
the chip select of each attached device into one of the four layout registers.
The bulk of the programming is actually applied to the GPMI through PIO operations
embedded in DMA command structures. The DMA will perform all the requisite handshaking
with the GPMI interface to negotiate the address portion of the transfer, then the BCH will
handle all the movement of data from memory to the GPMI (writes) or the GPMI to memory
(reads). The BCH will direct all data blocks to the buffer pointed to by the
PAYLOAD_BUFFER and the metadata will be written to the AUXILIARY_BUFFER.
Both of these registers are located in the GPMI PIO data space and are communicated to
the BCH hardware at the beginning of the transfer. Thus, the normal multi-NAND DMA
based device interleaving is preserved, that is, four NANDs on four separate chip selects
can be scheduled for read or write operations using the BCH. Whichever channel finishes
its ready wait first and enters the DMA arbiter with its lock bit set owns the GPMI command
interface and through it owns the BCH resources for the duration of its processing.
16.4.1 BCH Encoding for NAND Writes
The BCH encoder flowchart in
and using the BCH encoder. This flowchart shows how to use the BCH block with the
GPMI.
To use the BCH encoder with the GPMI's DMA, create a DMA command chain containing
ten descriptor structures, as shown in
example that follows it in
following tasks:
Freescale Semiconductor, Inc.
1. Disable the BCH block (in case it was enabled) and issue NAND write setup command
2. Configure and enable the BCH and GPMI blocks to perform the NAND write.
3. Disable the BCH block and issue NAND write execute command byte (under CLE).
4. Wait for the NAND device to finish writing the data by watching the ready signal.
5. Check for NAND timeout through PSENSE.
byte (under CLE) and address bytes (under ALE).
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
DMA Structure Code
Figure 16-6
Figure 16-8
shows the detailed steps involved in programming
Example. The ten descriptors perform the
Chapter 16 20-BIT Correcting ECC Accelerator (BCH)
and detailed in the DMA structure code
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