MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 368

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
368
CHANNEL
CHANNEL
FREEZE_
RESET_
31 16
Field
15 0
Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state.
The bit is reset after the channel resources are cleared.
0x0001
0x0002
0x0004
0x0008
0x0010
0x0020
0x0040
0x0080
0x0100
0x0200
0x0400
0x0800
0x1000
0x2000
Setting a bit in this field will freeze the DMA channel associated with it. This field is a direct input to the DMA
channel arbiter. When frozen, the channel is denied access to the central DMA resources. Note: 1. DMA
PIO write to associated peripheral is not supported when Freeze bit is set, and use ARM instead to configure
peripheral. 2. After FREEZE bit is set, no more access, neither AHB access to memory nor APB access to
peripherals, will be allowed by arbiter. But, there might be on-going channel access exactly when FREEZE
bit is set, either INCR8/INCR4/SINGLE AHB access or APB peripheral access, this on-going access will not
be affected by FREEZE bit and will finish as normal. That is to say, setting FREEZE bit might not freeze
channel access immediately, it only freezes further channel access, and you have to wait a while to freeze
channel access completely. To make sure that there is no more access from freezed channel, channel state
machine should be checked by reading channel DEBUG1 register, wait till state stunk at any of IDLE,
READ_REQ, WRITE, or CHAIN_WAIT.
0x0001
0x0002
0x0004
0x0008
0x0010
0x0020
0x0040
0x0080
0x0100
0x0200
0x0400
0x0800
0x1000
0x2000
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_APBH_CHANNEL_CTRL field descriptions
SSP0 —
SSP1 —
SSP2 —
SSP3 —
NAND0 —
NAND1 —
NAND2 —
NAND3 —
NAND4 —
NAND5 —
NAND6 —
NAND7 —
HSADC —
LCDIF —
SSP0 —
SSP1 —
SSP2 —
SSP3 —
NAND0 —
NAND1 —
NAND2 —
NAND3 —
NAND4 —
NAND5 —
NAND6 —
NAND7 —
HSADC —
LCDIF —
Description
Freescale Semiconductor, Inc.