MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1073

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

1. The response will only be sent if all of the older write responses have been issued for any thread ID on that port.
axi_AWCACHE [0] comes from the standard AXI bus signal and the axi_AWCOBUF is
configured by user-defined register “BRESP_TIMING” (Bit [0] of register
HW_DRAM_CTL00).
Note that in the “AHB-AXI Bridge”, axi_AWCACHE [0] is tied-off to 1, and the
axi_AWCOBUF is tied-off to 0. Therefore, the write reponse type of AXI Interface 1~3 is
forced to “Standard Bufferable Write.”
14.4.6 AHB Register Port
The register port is an independent AHB port to the EMI. This port operates asynchronously.
The register port only supports the AHB SINGLE burst type.
The register port only supports transfer types of NONSEQ or IDLE. There is no support
for INCR or WRAP burst types. There is no support for SEQ or BUSY transfer types.
14.4.7 AXI Transactions
The AXI Interface supports burst tpye of INCR and WRAP.
The AXI Interface supports burst length of 1-16 beats.
14.4.8 Exclusive Access
Note: The exclusive access option is an AXI-specific feature that requires use of the
axi_ARLOCK and axi_AWLOCK signals. Therefore, this feature is only relevant for the
native AXI ports.
The exclusive access feature allows a master to monitor if a memory area has been altered
since its last read. Exclusive access does not imply that the memory area is locked; other
thread IDs of that port, or other ports, may access the area for reads or writes even though
an exclusive access exists. If any writes occur to a memory area with a valid exclusive
access request, the master will lose exclusivity and be informed of this status when it attempts
to write to the area again. A loss of exclusivity does not trigger an interrupt or any error
conditions; however, the AXI protocol requires that the write data is not written to memory
Freescale Semiconductor, Inc.
axi_AWCACHE[0]
1
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
axi_AWCOBUF
1
Coherent bufferable write command. Response is ready when the command
has been accepted by the command queue in the core logic.This guarantees
data coherency across all ports but reduces the overall write response latency
relative to the non-bufferable option.
Response Information
1
Chapter 14 External Memory Interface (EMI)
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