MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1071

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

14.4.4 AXI Interface FIFOs
Each programmable port contains four FIFOs for commands, read data, write data and
response synchronization. The response synchronization FIFOs are only used when operating
in asynchronous mode. In addition to the FIFOs, each port contains a storage array to hold
the read and write responses. The depths and clock domain relativity of the FIFOs and the
array are shown in
The five channels of traffic and their relationship to the port FIFOs are shown below.
Freescale Semiconductor, Inc.
• 2:1 Port:Core Pseudo-Synchronous (‘b01)
• Asynchronous (‘b00)
The port operates at half of the frequency of the emi_clk frequency, with clocks that
are aligned in phase. One stage of the two-stage synchronization logic of the FIFOs
will be utilized to synchronize commands, write data and read data to the appropriate
clock domain.
Reserved. Do not select this mode. Select “Asynchronous” instead.
The port frequency is twice the emi_clk frequency, although the clocks are aligned in
phase. One stage of the two-stage synchronization logic of the FIFOs will be utilized
to synchronize commands, write data, and read data to the appropriate clock domain.
The AXI bus and the core logic operate on clocks that are mismatched in frequency
and phase. The AXI port FIFOs use two stages of synchronization logic to synchronize
commands, write data, and read data to the appropriate clock domain.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table
14-4.
Chapter 14 External Memory Interface (EMI)
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