MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1781

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

28.2.4 Channel 2 Analog Enable Function
The output generation for channel 2 is slightly different than shown in
channel, there is an additional enable that is controlled from the analog LRADC block. This
signal is synchronized in the XTAL domain and ANDed with the PWM ENABLE bit. So,
in this case, either enable source can disable the output. Also, this analog enable control
signal can be disabled through the PWM2_ANA_CTRL_ENABLE bit in the
HW_PWM_CTRL register. When disabled, Channel 2 behaves identically to the other
channels.
28.2.5 Channel Output Cutoff Using Module Clock Gate
Whenever the clkgate is enabled (gated) the output from all PWM channels is hi-Z. If the
clock gate is asserted while PWM is enabled and generating an output signal the output is
immediately disabled. This will not affect the current state, programming or enables of the
pwm channels themselves. When the clkgate is de-asserted, the PWM outputs will resume
according to their programmed parameters and current states. Therefore glitches on the
enabled channel outputs will likely occur when the clkgate state is changed. All 8 channels
will function identically in this regard.
28.3 Behavior During Reset
A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set
CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See
Correct Way to Soft Reset a Block
CLKGATE bit fields.
28.4 Programmable Registers
PWM Hardware Register Format Summary
Freescale Semiconductor, Inc.
8006_4000
8006_4010
8006_4020
8006_4030
Absolute
address
(hex)
PWM Control and Status Register (HW_PWM_CTRL)
PWM Channel 0 Active Register (HW_PWM_ACTIVE0)
PWM Channel 0 Period Register (HW_PWM_PERIOD0)
PWM Channel 1 Active Register (HW_PWM_ACTIVE1)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Register name
HW_PWM memory map
for additional information on using the SFTRST and
Chapter 28 Pulse-Width Modulator (PWM) Controller
(in bits)
Width
32
32
32
32
Access
R/W
R/W
R/W
R/W
FFC0_0000h
Reset value
0000_0000h
0000_0000h
0000_0000h
Figure
28-5. In this
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