MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 419

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

6.5.49 AHB to APBH DMA Channel 5 Debug Information
This register gives debug visibility for the APB and AHB byte counts for DMA Channel
5.
This register allows debug visibility of the APBH DMA Channel 5.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
AHB_BYTES
APB_BYTES
31
0
31 16
Field
15 0
30
0
Field
29
0
(HW_APBH_CH5_DEBUG2)
HW_APBH_CH5_DEBUG2
28
0
This value reflects the current number of APB bytes remaining to be transfered in the current transfer.
This value reflects the current number of AHB bytes remaining to be transfered in the current transfer.
27
0
HW_APBH_CH5_DEBUG1 field descriptions (continued)
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
APB_BYTES
0
0x0D
0x0E
0x0F
0x14
0x15
0x1C
0x1D
0x1E
0x1F
24
HW_APBH_CH5_DEBUG2 field descriptions
0
READ_REQ — During DMA Read transfers, the state machine waits in this state until the
AHB master arbiter accepts the request from this channel.
CHECK_CHAIN — Upon completion of the DMA transfers, this state checks the value of
the Chain bit and branches accordingly.
XFER_COMPLETE — The state machine goes to this state after the DMA transfers are
complete, and determines what step to take next.
TERMINATE — When a terminate signal is set, the state machine enters this state until the
current AHB transfer is completed.
WAIT_END — When the Wait for Command End bit is set, the state machine enters this
state until the DMA device indicates that the command is complete.
WRITE_WAIT — During DMA Write transfers, the state machine waits in this state until the
AHB master completes the write to the AHB memory space.
HALT_AFTER_TERM — If HALTONTERMINATE is set and a terminate signal is set, the
state machine enters this state and effectively halts. A channel reset is required to exit this
state
CHECK_WAIT — If the Chain bit is a 0, the state machine enters this state and effectively
halts.
WAIT_READY — When the NAND Wait for Ready bit is set, the state machine enters this
state until the GPMI device indicates that the external device is ready.
23
0
22
0
21
0
8000_4000h base + 390h offset = 8000_4390h
20
0
19
0
18
0
17
0
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
16
0
15
0
Description
14
0
Description
13
0
12
0
11
0
10
0
AHB_BYTES
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
419
0
0