MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1002

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
13.2 Operation
The top-level DCP module contains the AXI master, APB slave bus interface units, the
main control block and FIFO, and any encryption or hashing blocks included with the
design.
The controller manages the fetching of work blocks, the fetching/storing of context
information when switching between chain pointers, and the data flow through FIFO, SHA,
and AES blocks. Data entering the block from the AXI master is placed in the FIFO for
consumption by the cipher block. After the cipher module has finished its operation, data
is placed back into the FIFO and stored back to memory through the AXI master. When
hashing is enabled, the SHA block takes its inputs from the bus side of the FIFO to allow
it to operate without waiting for the cipher block to complete. The APB slave provides all
register controls and interfaces mainly with the control block.
13.2.1 Memory Copy, Blit, and Fill Functionality
In its most basic operation, the DCP supports moving unmodified data from one place in
system memory to another. This functionality is referred to as memcopy, because it operates
only on memory and it copies data from one place to another. Typical uses of memcopy
might be for fast virtual memory page moves or repositioning data blocks in memory.
Memcopy buffers can be aligned to any memory address and can be of any length (byte
granularity). For best performance, buffers should be word-aligned, although the DCP
includes enhancements to improve performance for unaligned cases.
The DCP also has the ability to perform basic blit operations that are typical in graphics
operations. To specify a blit, the control packet must have the ENABLE_BLIT bit set in
the packet control register. Blit source buffers must be contiguous. The output destination
buffer for a blit operation is defined as a "M runs of N bytes" that define a rectangular region
in a frame buffer. For blit operations, each line of the blit may consist of any number of
bytes. After performing a run, the DCP updates the destination pointer such that the next
destination address falls on the pixel below the start of the previous run operation. This is
performed by incrementing the starting pointer by the frame buffer width, which is specified
in Control1 field.
In addition to being able to copy data within memory, the DCP also provides a fill operation,
where source data comes not from another memory location, but from an internal register
(the source buffer address in the control packet). This is performed whenever the
CONSTANT_FILL flag is set in the packet control register. This feature may be used with
memcopy to prefill memory with a specified value or during a blit operation to fill a
rectangular region with a constant color.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1002
Freescale Semiconductor, Inc.