MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1139

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

14.8.33 DRAM Control Register 35 (HW_DRAM_CTL35)
This is a DRAM configuration register.
Address:
Freescale Semiconductor, Inc.
Reset
Reset
NO_CMD_INIT
SREFRESH_
OBSOLETE
Bit
Bit
W
W
PWRUP_
R
R
RSVD3
RSVD2
31 24
23 17
Field
EXIT
15 9
Field
16
8
31
15
0
0
HW_DRAM_CTL35
30
14
0
0
Always write zeroes to this field.
Always write zeroes to this field.
Allow powerup through self-refresh instead of full memory initialization.
Allows controller to exit power-down mode by executing a self-refresh exit instead of the full memory
initialization. This parameter provides a means to skip full initialization when the DRAM devices are in a
known self-refresh state.
'b0 = Disabled
'b1 = Enabled
Always write zeroes to this field.
Disable DRAM cmds until TDLL has expired during initialization.
Disables DRAM commands until DLL initialization is complete and tdll has expired.
'b0 = Issue only REF and PRE commands during DLL initialization of the DRAM devices. If PRE commands
are issued before DLL initialization is complete, the command will be executed immediately, and then the
DLL initialization will continue.
'b1 = Enable interrupting an auto pre-charge operation on a different bank.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DRAM_CTL34 field descriptions (continued)
RSVD2
OBSOLETE
28
12
0
0
800E_0000h base + 8Ch offset = 800E_008Ch
HW_DRAM_CTL35 field descriptions
27
11
0
0
26
10
0
0
25
0
0
9
24
0
0
8
Description
Description
23
0
0
7
22
0
0
6
RSVD1
Chapter 14 External Memory Interface (EMI)
21
0
5
0
RSVD3
20
0
4
0
19
0
0
3
INITAREF
18
0
0
2
17
0
0
1
1139
16
0
0
0