MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1137

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

14.8.32 DRAM Control Register 34 (HW_DRAM_CTL34)
This is a DRAM configuration register.
Address:
Freescale Semiconductor, Inc.
Reset
CONCURRENTAP
OBSOLETE
Bit
W
R
RSVD2
RSVD1
31 16
15 9
Field
7 1
AP
8
0
31
0
HW_DRAM_CTL34
30
0
Always write zeroes to this field.
Always write zeroes to this field.
Allow controller to issue cmds to other banks while a bank is in auto pre-charge.
Enables concurrent auto pre-charge. Some DRAM devices do not allow one bank to be auto pre-charged
while another bank is reading or writing. The JEDEC standard allows concurrent auto pre-charge. The
user should set this parameter if the DRAM device supports this feature.
'b0 = Concurrent auto pre-charge disabled.
'b1 = Concurrent auto pre-charge enabled.
Always write zeroes to this field.
Enable auto pre-charge mode of controller.
Enables auto pre-charge mode for DRAM devices.
This parameter may not be modified after the start parameter has been asserted.
'b0 = Auto pre-charge mode disabled. Memory banks will stay open until another request requires this
bank, the maximum open time (tras_max) has elapsed, or a refresh command closes all the banks.
'b1 = Auto pre-charge mode enabled. All read and write transactions must be terminated by an auto
pre-charge command. If a transaction consists of multiple read or write bursts, only the last command is
issued with an auto pre-charge.
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
RSVD4
28
0
HW_DRAM_CTL33 field descriptions
800E_0000h base + 88h offset = 800E_0088h
27
0
26
0
25
0
24
0
Description
23
0
22
0
Chapter 14 External Memory Interface (EMI)
21
0
RSVD3
20
0
19
0
18
0
17
0
1137
16
0