MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1737

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

In this way, the I2C_SCL clock is generated, with its low period determined by the device
with the longest clock low period and its high period determined by the one with the shortest
clock high period.
27.2.2.5 Master Mode Operation
The finite state machine for master mode operation is shown in
27-7.
the receive states,
of the optional stop state.
Table 27-10
27-3
performed using the restart technique.
Freescale Semiconductor, Inc.
Table 27-11. I
Table 27-13. I
ST
Table 27-10. I
Table 27-12. I
ST
ST
ST
defines each sub-address shown. The following read-after-write transactions are
SAD+W
Figure 27-4
SAD+W
SAD+W
SAD+R
through
SAK
2
C Transfer When the Interface as Master is Receiving >1 Byte of Data from
2
2
2
C Transfer When Master is Receiving >1 byte of Data from Slave Internal
C Transfer when Master is Receiving 1 Byte of Data from Slave Internal
C Transfer When Master is Transmitting 1 Byte of Data to Slave Internal
SAK
SUB
shows the generation of the optional start condition.
Figure 27-6
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
SAK
SAK
Table 27-13
SAK
SUB
SUB
DATA
SUB
shows the transmit states.
SAK
show examples of Master Mode I
SAK
SUB
MAK
Subaddress
SAK
Subaddress
Subaddress
SR
Slave
S A D + R
SAK
DATA
SUB
SAK
SR
DATA
Figure 27-7
MAK
SAK
SAD+R
MAK
Figure 27-4
DATA
SAK
DATA
DATA
2
C transactions.
shows the generation
MAK
Figure 27-5
DATA
Chapter 27 Inter IC (I2C)
NMAK
SAK
through
DATA
NMAK
NMAK
shows
Figure
Table
SP
SP
SP
SP
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