MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1953

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

initiates transmission from the PrimeCell UART. The data is prefixed with a start bit,
appended with the appropriate parity bit (if parity is enabled), and a stop bit. The resultant
word is then transmitted. Note: With the use of APB byte-enables you can write 1, 2, or 4
valid bytes sumultaneously to the TXFIFO. The invalid bytes will also take up space in the
TXFIFO. So every write cycle will consume 4 bytes in the TXFIFO. If TXFIFO is disabled,
you must only write the LSByte of the DATA register. For received words: 1) If the FIFOs
are enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed
onto the 12-bit wide receive FIFO; 2) if the FIFOs are not enabled, the data byte and status
are stored in the receiving holding register (the bottom word of the receive FIFO). The
received data bytes (up to 4) are read by performing reads from the 32-bit DATA register.
The status information can be read by a read of the UART Status register. The Overrun
Error bit is set to 1 if data is received and the receive FIFO is already full. This is cleared
to 0 once there is an empty space in the FIFO and a new character can be written to it. The
Break Error bit is set to 1 if a break condition was detected, indicating that the received data
input was held LOW for longer than a full-word transmission time (defined as start, data,
parity and stop bits). In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next
character is only enabled after the receive data input goes to a 1 (marking state), and the
next valid start bit is received. When the Parity Error bit is set to 1, it indicates that the
parity of the received data character does not match the parity selected as defined by bits 2
and 7 of the LCR_H register. In FIFO mode, this error is associated with the character at
the top of the FIFO. When the Framing Error bit is set to 1, it indicates that the received
character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is
associated with the character at the top of the FIFO.
Address:
Re-
Freescale Semiconductor, Inc.
set
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DATA
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HW_UARTAPP_DATA
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In DMA mode, up to 4 Received/Transmit characters can be accessed at a time. In PIO mode, only one
character can be accessed at a time. The status register contains the receive data flags and valid bits.
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i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
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HW_UARTAPP_DATA field descriptions
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8006_A000h base + 60h offset = 8006_A060h
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Description
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Chapter 30 Application UART (AUART)
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