MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2126

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
By default, the PXP color space coefficients are set to support the conversion of YUV data
to RGB data. If YCbCr input is present, software must change the coefficient registers
appropriately (see the register definitions for values). Software must also set the
YCBCR_MODE bit in the COEFF0 register to ensure proper conversion of YUV versus
YCbCr data.
34.2.5 Overlays
The PXP supports up to eight overlays that can be used to merge graphic data with video
(or other graphic data). Each overlay consists of a rectangular area that is a multiple of Ôn'
(where n is the block size) pixels in both the vertical and horizontal directions. Overlays
must also be located on NxN boundaries within the output image. As the PXP processes
each NxN macroblock, it determines if any of the enabled overlays cover the block and
then merges the overlay data with the background image as specified in the overlay's control
registers. If multiple overlays overlap for a given NxN block, the PXP will select the lowest
numbered one for the blending operation. If the desired affect is to blend the overlays
together, this can be accomplished as a multi-step process using the IN_PLACE functionality
(see
Each overlay can perform one of three classes of operations between the overlay and the
underlying background (S0) image: alpha blending, color keying, or raster operations.
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In-place
Rendering).
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 34-7. Pixel Pipeline Overlay Support
parameters. Overlay 0 has the highest priority (effectively it is the highest in the stacking order)
The S0 buffer and each overlay can be placed within the output buffer using their XBASE and
YBASE registers and the dimensions of each region are set using their WIDTH and HEIGHT
0,0
0,1
0,2
0,3
0,4
Overlays can be blended with the background or S0 planes, but not with each other.
Effectively only a single overlay is active for each 8x8 pixel block.
and the S0 buffer and background color have the lowest priority.
1,0
1,1
1,2
1,3
1,4
HEIGHT=2
XBASE=1
YBASE=3
WIDTH=2
OL0
2,0
2,1
2,2
2,3
2,4
Output Buffer
HEIGHT=3
Background Color
WIDTH=6
XBASE=0
YBASE=1
S0 Buffer
WIDTH=4 HEIGHT=1
XBASE=2 YBASE=3
3,0
3,1
3,2
3,3
3,4
OL1
HEIGHT=5
WIDTH=1
XBASE=4
YBASE=0
OL2
4,1
4,4
4,0
4,2
4,3
5,0
5,1
5,2
5,3
5,4
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