MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1344

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
17.10.15 SD/MMC Double Data Rate Control Register
SD/MMC Double Data Rate Control Register.
This register provides programmability in DDR mode for data output timing and data
formats.
Address:
1344
Reset
Reset
TXCLK_DELAY_
DMA_BURST_
NIBBLE_POS
Bit
Bit
W
W
R
R
RSVD0
RESP3
31 30
TYPE
TYPE
Field
31 0
Field
29 2
1
0
31
15
BURST_
0
0
DMA_
TYPE
HW_SSP_DDR_CTRL
30
14
0
0
(HW_SSP_DDR_CTRL)
SD/MMC Long Response [127:96]
The field controls the number of APB transfers per DMA request. 2'b00: select one APB transfer per DMA
request
2'b01: select 4 APB transfers per DMA request. 2'b10: select 8 APB transfers per DMA request. 2'b11:
reserved
Reserved
This bit only applies in MMC 4-bit DDR transfers. 0: The two high nibbles of two odd and even bytes are
sent/received on a cycle(both edges), then the low nibbles of the odd and even bytes are sent/received on
the next cycle.
1: Two nibbles of every bytes are sent/received on a cycle.
This field specifies two delay methods of delaying SCK related to SSP TX data to serve the purpose of
obtaining better TX data setup time. Set this bit to 0 to choose the pre-set gate delay, which is approximately
5ns; set this bit to 1 to choose the SCK-coupled delay, which is 1/4 of SCK period.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_SSP_DDR_CTRL field descriptions
HW_SSP_SDRESP3 field descriptions
27
11
8001_0000h base + E0h offset = 8001_00E0h
0
0
26
10
0
0
RSVD0[15:2]
25
0
0
9
24
0
0
8
Description
Description
RSVD0[29:16]
23
0
0
7
22
0
0
6
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0