MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 875

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

10.8.15 SPDIF Clock Control Register (HW_CLKCTRL_SPDIF)
This register controls the clock gate on the SPDIF clock, CLK_PCMSPDIF.
EXAMPLE
HW_CLKCTRL_SPDIF_WR(BF_CLKCTRL_SPDIF_CLKGATE(1));
Address:
Freescale Semiconductor, Inc.
Reset
Reset
DIV_FRAC_EN
CLKGATE
Bit
Bit
W
W
RSRVD2
RSRVD1
R
R
28 11
BUSY
Field
Field
9 0
DIV
30
29
10
31
31
15
1
0
HW_CLKCTRL_SPDIF
30
14
0
0
Always set to zero (0).
This read-only bit field returns a one when the clock divider is busy transfering a new divider value across
clock domains.
Always set to zero (0).
1 = Enable fractional divide. 0 = Enable integer divide.
The GPMI clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_io) by the
value in this bit field. This field can be programmed with a new value only when CLKGATE = 0.
NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0.
CLK_PCMSPDIF Gate. If set to 1, CLK_PCMSPDIF is gated off. 0: CLK_PCMSPDIF is not gated. When
this bit is modified, or when it is high, the SPDIF rate change field should not change its value. The SPDIF
rate change field can change ONLY when this clock gate bit field is low.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_CLKCTRL_GPMI field descriptions (continued)
28
12
0
0
HW_CLKCTRL_SPDIF field descriptions
27
11
0
0
8004_0000h base + E0h offset = 8004_00E0h
26
10
0
0
25
0
0
9
RSRVD[15:0]
24
0
0
8
RSRVD[30:16]
Description
Description
Chapter 10 Clock Generation and Control (CLKCTRL)
23
0
0
7
22
0
0
6
21
0
5
0
20
0
4
0
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0
875