MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 95
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
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As shown below, the i.MX28 uses a three-layer AHB, one AXI 64bit bus and two APB
buses (APBH and APBX).
1.3.2.1 AXI Bus Segments
The AXI0 bus-segment on the i.MX28 provides several high-bandwidth/performance-critical
peripherals, a tightly-coupled and efficient interface to Port-0 of the external memory
controller. The peripherals are as follows:
Freescale Semiconductor, Inc.
• AXI is the highest-performance AMBA bus that supports de-coupled R/W channels,
• AHB is a higher-performance bus that supports multiple masters such as the CPU and
• The APB is a lower-speed peripheral bus.
• DCP (Crypto/Memcpy)
ARM 926 32K+16K
S
32K SRAM
32K SRAM
32K SRAM
32K SRAM
USB1
USB0
ETM9 Coresight
multiple outstanding transactions, and out-of-order data capability. This leads to higher
performance and more efficient use of external memory.
DMA controllers.
(D$) ( I$)
S (MAC0)
S (MAC1)
S (SW)
S
M
S
M
(word intlv)
Controller
OCRAM
2xMAC
Switch
+
M
M
Data R/Write
Instr Fetch
uDMA0
uDMA1
32 AHB
32 AHB
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
M
M
EMI
ASYNCH
Figure 1-2. i.MX28 SOC System Buses
SYNC/
32
DDR2-400, LV -DDR2-400, LP-DDR1-400 16-bit
ASYNCH
SYNC/
32
ASYNCH
SYNC/
32
32
M
S
M
S
AHB0
S
S
S
S
DRAM_REGS
OCROM
ASYNCH
APBX Bridge/DMA
APBH Bridge/DMA
DFLPT
SYNC/
128K
64
64
64
64
64
64
M
M
M
M
S
HSADC
PERFMON
CAN0
CAN1
LCDIF
DCP
BCH
PXP
ASYNC
M
M
S
S
S
S
S
DIGCTL
OCOTP
PINCTRL
ETM9
ICOLL
GPMI
SSP0
SSP1
SSP2
SSP3
slave
Chapter 1 Product Overview
AUART 0
AUART 1
AUART 2
AUART 3
AUART 4
DUART
SAIF0
SAIF1
I2C0
I2C1
POWER
TIMROT
LRADC
CLKCTRL
SPDIF
UTM1
UTM2
PWM
RTC
TX
95
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