MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 430

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
6.5.60 APBH DMA Channel 7 Buffer Address Register
The APBH DMA Channel 7 buffer address register contains a pointer to the data buffer for
the transfer. For immediate forms, the data is taken from this register. This is a byte address
which means transfers can start on any byte boundary.
430
HALTONTERMINATE
WAIT4ENDCMD
IRQONCMPLT
SEMAPHORE
COMMAND
RSVD1
RSVD0
CHAIN
11 9
Field
5 4
1 0
8
7
6
3
2
(HW_APBH_CH7_BAR)
HW_APBH_CH7_CMD field descriptions (continued)
Reserved, always set to zero.
A value of one indicates that the channel immediately terminates the current descriptor and halts the
DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the
channel if the terminate signal is set, but the channel continues as if the count had been exhausted,
meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD.
A value of one indicates that the channel waits for the end of command signal to be sent from the
APBX device to the DMA before starting the next DMA command.
A value of one indicates that the channel decrements its semaphore at the completion of the current
command structure. If the semaphore decrements to zero, then this channel stalls until software
increments it again.
Reserved, always set to zero.
A value of one indicates that the channel will cause its interrupt status bit to be set upon completion
of the current command, i.e. after the DMA transfer is complete.
A value of one indicates that another command is chained onto the end of the current command
structure. At the completion of the current command, this channel will follow the pointer in
HW_APBX_CH3_CMDAR to find the next command.
This bitfield indicates the type of current command:
00- NO DMA TRANSFER
01- write transfers, that is, data sent from NAND3 (APB PIO Read) to the system memory (AHB
master write).
10- read transfer
11- SENSE
0x0
0x1
0x2
0x3
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
NO_DMA_XFER — Perform any requested PIO word transfers but terminate command before
any DMA transfer.
DMA_WRITE — Perform any requested PIO word transfers and then perform a DMA transfer
from the peripheral for the specified number of bytes.
DMA_READ — Perform any requested PIO word transfers and then perform a DMA transfer
to the peripheral for the specified number of bytes.
DMA_SENSE — Perform any requested PIO word transfers and then perform a conditional
branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense
is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true.
Description
Freescale Semiconductor, Inc.