MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1306

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
Address:
1306
Reset
Reset
PAYLOAD_FLAG
KES_DEBUG_
KES_DEBUG_
KES_DEBUG_
KES_DEBUG_
SYNDROME_
SHIFT_SYND
ROM_BIST_
ROM_BIST_
COMPLETE
Bit
Bit
W
W
SYMBOL
MODE4K
ENABLE
R
R
RSVD1
31 27
24 16
Field
26
25
15
14
13
31
15
0
0
HW_BCH_DEBUG0
30
14
0
0
Reserved, always set these bits to zero.
Software may initiate a ROM BIST operation by toggling this bit from a zero to a one. When the operation
is complete, the ROM_BIST_COMPLETE bit will be set and the ROM's CRC value will be available in the
DEBUG data register.
This bit will be set after a BIST operation completes, at which time the ROM CRC is available in the
DBGKESREAD register. The CRC value will be cleared after the BIST_ENABLE bit is cleared.
The 9 bit value in this bit field will be shifted into the syndrome register array at the input of the KES engine
whenever HW_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled.
0x0
0x1
Toggling this bit causes the value in HW_BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the
syndrome register array at the input to the KES engine. After shifting in 16 symbols, one can kick off both
KES and CF cycles by toggling HW_BCH_DEBUG0_KES_DEBUG_KICK. Be sure to set
KES_BCH_DEBUG0_KES_STANDALONE mode to 1 before kicking.
When running the stand alone debug mode on the error calculator, the state of this bit is presented to the
KES engine as the input payload flag.
0x1
0x1
When running the stand alone debug mode on the error calculator, the state of this bit is presented to the
KES engine as the input mode (4K or 2K pages).
0x1
0x1
RSVD1
29
13
0
0
NORMAL — Bus master address generator for synd_gen writes operates normally.
TEST_MODE — Bus master address generator always addresses last four bytes in Auxilliary block.
DATA — Payload is set for 512 byte data block.
AUX — Payload is set for 65 or 19 byte auxilliary block.
4k — Mode is set for 4K NAND pages.
2k — Mode is set for 2K NAND pages.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_BCH_DEBUG0 field descriptions
8000_A000h base + 100h offset = 8000_A100h
27
11
0
0
26
10
0
0
25
0
0
9
24
0
0
8
Description
23
0
0
7
RSVD0
KES_DEBUG_SYNDROME_SYMBOL
22
0
0
6
21
0
5
0
20
DEBUG_REG_SELECT
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0