MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 348

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

APBH DMA
If the wait-for-end-command bit (WAIT4ENDCMD) is set in a command structure, then
the DMA channel waits for the device to signal completion of a command by toggling the
endcmcd signal before proceeding to load and execute the next command structure. Then,
if DECREMENT_SEMAPHORE is set, the semaphore will be decremented after the end
command is seen.
A detailed bit-field view of the DMA command structure is shown in the following table,
which shows a field that specifies the number of bytes to be transferred by this DMA
command. The transfer-count mechanism is duplicated in the associated peripheral, either
as an implied or as a specified count in the peripheral.
Table 6-3. DMA Channel Command Word in System Memory
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
NEXT_COMMAND_ADDRESS
Number PIO
Number DMA Bytes to Transfer
Words to
Write
DMA Buffer or Alternate CCW
Zero or More PIO Words to Write to the Associated Peripheral Starting at its Base Address on the APBH Bus
Figure 6-2
also shows the CHAIN bit in bit 2 of the second word of the command structure.
This bit is set to 1, if the NEXT_COMMAND_ADDRESS contains a pointer to another
DMA command structure. If a null pointer (0) is loaded into the
NEXT_COMMAND_ADDRESS, it is not detected by the DMA hardware. Only the CHAIN
bit indicates whether a valid list exists beyond the current structure.
If the IRQ_COMPLETE bit is set in the command structure, then the last act of the DMA
before loading the next command is to set the interrupt-status bit corresponding to the current
channel. The sticky interrupt request bit in the DMA CSR remains set until cleared by the
software. It can be used to interrupt the CPU.
The NAND_LOCK bit is monitored by the DMA channel arbiter. After a NAND channel
(from channel 4 to channel 11) succeeds in the arbiter with its NAND_LOCK bit set, then
the arbiter ignores the other seven NAND channels until a command is completed in which
the NAND_LOCK is not set. Notice that the semantic here is that the NAND_LOCK state
is to limit scheduling of a non-locked DMA. A DMA channel can go from unlocked to
locked in the arbiter at the beginning of a command when the NAND_LOCK bit is set.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
348
Freescale Semiconductor, Inc.