MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2087

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
OVERFLOW_IRQ
VSYNC_EDGE_
VSYNC_EDGE_
BUSY_ENABLE
DONE_IRQ_EN
UNDERFLOW_
UNDERFLOW_
CUR_FRAME_
CUR_FRAME_
OVERFLOW_
DONE_IRQ
RSRVD0
MODE86
IRQ_EN
IRQ_EN
IRQ_EN
Field
IRQ
IRQ
7 3
15
14
13
12
11
10
9
8
2
1
This bit is set to enable an overflow interrupt in the TXFIFO in the write mode.
This bit is set to enable an underflow interrupt in the TXFIFO in the write mode.
This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state.
This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the
VSYNC and DOTCLK modes, or the beginning of every field in DVI mode.
This bit is set to indicate that an interrupt is requested by the LCDIF block. This bit is cleared by software
by writing a one to its SCT clear address. A latency FIFO (LFIFO) overflow in the write mode
(system/VSYNC/DOTCLK/DVI mode) was detected, data samples have been lost.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the LCDIF block. This bit is cleared by software
by writing a one to its SCT clear address. A TXFIFO underflow in the write mode
(system/VSYNC/DOTCLK/DVI mode) was detected. Could produce an error in the DOTCLK / DVI modes.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the LCDIF block. This bit is cleared by software
by writing a one to its SCT clear address. It indicates that the hardware has completed transmitting the
current frame and is in the vertical blanking period in the DOTCLK/DVI modes. In the VSYNC and system
modes, this IRQ is asserted at the end of the data transfer indicated by HW_LCDIF_TRANSFER_COUNT
register.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the LCDIF block. This bit is cleared by software
by writing a one to its SCT clear address. It is set whenever the leading VSYNC edge is detected in the
VSYNC and DOTCLK modes. In the DVI mode, it is asserted every time the block enters a new field.
0x0
0x1
Reserved bits. Write as 0.
This bit enables the use of the interface's busy signal input. This should be enabled for LCD controllers that
implement a busy line (to stall the LCDIF from sending more data until ready). Otherwise this bit should be
cleared.
0x0
0x1
This bit is used to select between the 8080 and 6800 series of microprocessor modes. This bit should only
be changed when RUN is 0.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
BUSY_DISABLED — The busy signal from the LCD controller will be ignored.
BUSY_ENABLED — Enable the use of the busy signal from the LCD controller.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_LCDIF_CTRL1 field descriptions (continued)
Description
Chapter 33 LCD Interface (LCDIF)
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