MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2265

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface
The Gain_correction corrects a mean gain error in the temperature conversion and should
be 1.012. After this correction factor, the three-sigma error of the temperature sensor should
be within ± 1.5% in degrees Kelvin. Additionally, the temperature sampling has a three-sigma
sample-to-sample variation of 2 degrees Kelvin. If desired, this error can be removed by
oversampling and averaging the temperature result.
Prior to starting a battery charge cycle, the internal die temperature sensing could be used
for an approximate ambient temperature. During high-current battery charging, the
temperature sensor can be used as extra protection to avoid excessive die temperatures (to
reduce the charging current).
38.2.3 Scheduling Conversions
The APBX clock domain logic schedules conversions on a per-channel basis and handles
interrupt processing back to the CPU. Each of the eight virtual channels has its own interrupt
request enable bit and its own interrupt request status bit.
A schedule request bit, HW_LRADC_CTRL0_SCHEDULE, exists for each virtual channel.
Setting this bit causes the LRADC to schedule a conversion for that virtual channel. Each
virtual channel schedule bit is sequentially checked and, if scheduled, causes a conversion.
The schedule bit is cleared upon completion of a successive approximation conversion, and
its corresponding interrupt request status bit is set. Therefore, software controls how often
a conversion is requested. As each scheduled channel is converted, its interrupt status bit
is set and its schedule bit is reset.
There is a mechanism to continuously reschedule a conversion for a particular virtual
channel. With set/clear/toggle addressing modes, independent threads can request conversions
without needing any information from unrelated threads using other channels. Setting a
schedule bit can be performed in an atomic way. Setting a group of four channel-schedule
bits can also be performed atomically. The LRADC scheduler is round-robin. It snapshots
all schedule bits at once, and then processes them in sequence until all are converted. It then
monitors the schedule bits. If any schedule bits are set, it snapshots them and starts a new
conversion operation for all scheduled channels. Thus, one can set the schedule bits for four
channels on the same clock edge. The channel with the largest channel number is converted
last and has its interrupt status bit set last. If that channel is the only one of the four with an
interrupt enable bit set, then it interrupts the ARM after all four channels have been converted,
effectively ganging four channels together.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
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