MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 511

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

7.5.1 AHB to APBX Bridge Control Register 0 (HW_APBX_CTRL0)
The APBX CTRL 0 provides overall control and IRQ status of the AHB to APBX bridge
and DMA.
HW_APBX_CTRL0: 0x000
HW_APBX_CTRL0_SET: 0x004
HW_APBX_CTRL0_CLR: 0x008
HW_APBX_CTRL0_TOG: 0x00C
This register contains softreset, clock gating bits.
Address:
7.5.2 AHB to APBX Bridge Control Register 1 (HW_APBX_CTRL1)
The APBX CTRL 1 provides channel complete IRQ status of the AHB to APBX bridge
and DMA.
Freescale Semiconductor, Inc.
Reset
Reset
CLKGATE
Bit
Bit
W
W
SFTRST
R
R
RSVD0
Field
29 0
31
30
31
15
1
0
HW_APBX_CTRL0
30
14
1
0
Set this bit to zero to enable normal APBX DMA operation. Set this bit to one (default) to disable clocking
with the APBX DMA and hold it in its reset (lowest power) state. This bit can be turned on and then off to
reset the APBX DMA block to its default state.
This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block.
Reserved, always set to zero.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
8002_4000h base + 0h offset = 8002_4000h
HW_APBX_CTRL0 field descriptions
27
11
0
0
26
10
0
0
25
0
0
9
Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA)
RSVD0[15:0]
24
0
0
8
Description
RSVD0[29:16]
23
0
0
7
22
0
0
6
21
0
5
0
20
0
4
0
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0
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