MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1634

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Magic Packet Detection
26.3.10 Magic Packet Detection
26.3.10.1 Overview
Magic Packet detection is used to wake up a node that is put in the power down mode by
the node management agent. Magic Packet detection is supported only if the MAC is
configured in sleep mode.
26.3.10.2 Sleep Mode
To put the MAC in sleep mode, the configuration ECR(SLEEP) should be set to °Æ1°Ø.
At the same time, ECR(MAGIC_ENA) should be set to 1, to enable magic packet detection.
In addition, when the external input pin ipg_stop is asserted, sleep mode is entered also,
without affecting the ECR register bits.
When the Core is in sleep mode:
The MAC receive logic is kept in normal mode but it ignores all traffic from the line except
Magic Packets, which are detected so that a remote agent can wake up the node.
26.3.10.3 Magic Packet Detection
The Core is designed to detect Magic Packets (see 5.3 page 30) with the destination address
set to:
When a Magic Packets is detected, the interrupt bit EIR(WAKEUP) is asserted and none
of the statistic registers is incremented.
In addition, the external pin magic_det is asserted and held asserted until the magic packet
detection is disabled or the sleep mode is cancelled.
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• The MAC transmit logic is disabled.
• The Core FIFO receive / transmit functions are disabled.
• Any Multicast address.
• The Broadcast address.
• The Unicast address programmed in the Core registers PADDR1 / PADDR2.
• If enabled, to any of the Unicast addresses programmed in the Core supplemental MAC
address registers SMAC_0.. to SMAC_3.. .
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.