MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 988

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

NAND Boot Mode
In order to preserve the BI (bad block information), flash updater or gang programmer
applications need to swap Bad Block Information (BI) data to byte 0 of metadata area for
every page before programming NAND Flash. ROM when loading firmware, copies back
the value at metadata[0] to BI offset in page data. The following figure shows how the
factory bad block marker is preserved.
Bad block information at
column address 2048
64B
2KB Main area
spare
512 main
512 main
512 main
512 main
parity
parity
parity
parity
metadata
th
Bad block information at 4
block’s data area
Swap byte
Figure 12-13. Factory Bad Block Marker Preservation
In the FCB structure, there are two elements m_u32BadBlockMarkerByte and
m_u32BadBlockMarkerStartBit to indicate the byte offset and start bit of BI. ROM will
use 8 bits from start bit as BI.
The DBBT structure is contained within a block and is discussed in more detail below. The
figure below depicts the layout of the Discovered Bad Block Table block. The first 8K are
reserved for the DBBT Header. The following pages are used by the DBBT for each NAND.
The Bad Block table for each NAND begins on a 2 KB boundary that coincides with current
NAND page sizes and is a subset of future NAND page sizes. The BBT can extend beyond
2K, which is the purpose of the #2K_num, and translates to the number of 2K pages that
NAND0 through NAND3 require. In this way, the ROM can quickly index to the appropriate
NAND table.
Only the Bad Blocks for NAND0 are required and loaded.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
988
Freescale Semiconductor, Inc.