MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1929

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Address:
Re-
29.9.108 ENET SWI Interrupt Event Register (HW_ENET_SWI_EIR)
The event bits are latched. To clear a bit it must be written with 1. The bit will stay set if
the event condition persists.
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
BLOCKED2
31
31
RSRVD0
0
0
IDISC_
31 10
Field
31 0
Field
LRN
OD2
OD1
OD0
QM
30
30
9
8
7
6
5
0
0
29
29
0
0
HW_ENET_SWI_IDISC_BLOCKED2
833Ch
HW_ENET_SWI_EIR
28
28
0
0
ENET SWI Port 2 incoming frames discarded (after learning) as port is configured in blocking mod
Reserved bits. Write as 0.
Learning Record available in registers LNR_REC_0 and LNR_REC_1 (Signal ipi_lrn_int asserted).
Note: this interrupt can be very frequent on a heavy loaded network. It is not recommended to use this
interrupt source as interrupt but rather implement a slow background task polling the bit to perform learning.
Outgoing frames discarded due to output Queue congestion on Port 2 or port is disabled (PORT_ENA).
Asserts ipi_od2_int
Outgoing frames discarded due to output Queue congestion on Port 1or port is disabled (PORT_ENA).
Asserts ipi_od1_int
Outgoing frames discarded due to output Queue congestion on Port 0 or port is disabled (PORT_ENA).
Asserts ipi_od0_int
Low Memory Threshold. Asserted if the memory became congested and number of free cells dropped below
threshold QMGR_MINCELLS (Signal ipi_qm_int asserted).
27
27
0
0
26
26
0
0
HW_ENET_SWI_IDISC_BLOCKED2 field descriptions
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
23
23
0
0
HW_ENET_SWI_EIR field descriptions
22
22
800F_8000h base + 400h offset = 800F_8400h
0
0
RSRVD0
21
21
0
0
20
20
0
0
19
19
0
0
Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH)
18
18
800F_8000h base + 33Ch offset = 800F_
0
0
IDISC_BLOCKED2
17
17
0
0
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
0
0
7
7
0
0
6
6
0
1
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
1929
0
0
0
0