MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2118

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Pixel Pipeling (PXP) Overview
For the S0 plane, the PXP supports RGB images (unscaled) or color space conversion
(YUV->RGB) and scaling of YUV images. The S1 plane consists of up to eight overlay
regions consisting of 16- or 32-bit RGB data. The S0 and S1 planes may then be combined
by alpha blending, color key substitution, or raster operations (ROPs) to form the output
image. Finally, the resulting image may be clockwise rotated in 90 degree increments and/or
flipped horizontally and/or vertically. The PXP also supports letterboxing and interlacing
of progressive content (by writing alternate lines to different frame buffers).
The flow of data through the PXP is shown below.
34.1.1 Image Support
The PXP's S0 buffer supports the following image formats:
The PXP's S1 buffer supports the following image formats:
The PXP's output buffer supports:
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• 24-bit unpacked RGB (32bpp)
• 24-bit packed RGB (24bpp)
• 16-bit RGB in either 555 or 565 format
• 3-plane YUV/YCbCr in 4:2:0 or 4:2:2 format
• 2-plane YUV/YCbCr in 4:2:0 or 4:2:2 format
• 2-plane YUV/YCbCr in 4:2:2 format
• 32-bit RGB (with or without alpha)
• 16-bit RGB in either 555, 565, or 1555 (alpha)
• 32-bit RGB (with alpha)
• 24-bit packed RGB (24bpp)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 34-2. Pixel Pipeline (PXP) Data Flow
RGB
Y
U
V
Overlay
Scaler
CSC
S1
S0
alpha blending/
color key
S3
rotation
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