MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1029

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

HW_DCP_CHANNELCTRL_TOG: 0x02C
This register provides status feedback indicating the channel currently performing an
operation and which channels have pending operations.
EXAMPLE
Address:
Freescale Semiconductor, Inc.
Reset
Reset
channel 0
PRIORITY_
CH0_IRQ_
CHANNEL
CHANNEL
Bit
Bit
MERGED
ENABLE_
W
W
R
R
HIGH_
31 17
RSVD
Field
15 8
7 0
16
31
15
0
0
BW_DCP_CHANNELCTRL_ENABLE_CHANNEL(BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0);
HW_DCP_CHANNELCTRL 8002_8000h base + 20h offset = 8002_8020h
30
14
0
0
Reserved, always set to zero.
Indicates that the interrupt for channel 0 should be merged with the other interrupts on the shared dcp_irq
interrupt. When set to 0, channel 0's interrupt will be routed to the separate dcp_vmi_irq. When set to 1, the
interrupt will be routed to the shared DCP interrupt.
Setting a bit in this field causes the corresponding channel to have high-priority arbitration. High priority
channels will be arbitrated round-robin and will take precedence over other channels that are not marked
as high priority.
0x01
0x02
0x04
0x08
Setting a bit in this field will enabled the DMA channel associated with it. This field is a direct input to the
DMA channel arbiter. When not enabled, the channel is denied access to the central DMA resources.
0x01
0x02
0x04
0x08
HIGH_PRIORITY_CHANNEL
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
CH0 —
CH1 —
CH2 —
CH3 —
CH0 —
CH1 —
CH2 —
CH3 —
HW_DCP_CHANNELCTRL field descriptions
28
12
0
0
27
11
0
0
26
10
0
0
25
0
0
9
RSVD
24
0
0
8
Description
23
0
0
7
22
0
0
6
21
0
5
0
ENABLE_CHANNEL
Chapter 13 Data Co-Processor (DCP)
20
0
4
0
19
0
0
3
18
0
0
2
// enable
17
0
0
1
1029
16
0
0
0