MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2278
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
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Programmable Registers
HW_LRADC_CTRL2: 0x020
HW_LRADC_CTRL2_SET: 0x024
HW_LRADC_CTRL2_CLR: 0x028
HW_LRADC_CTRL2_TOG: 0x02C
The LRADC control register 2 provides control over the shared eight channel LRADC
converter. It allows software to independently schedule conversion cycles on any number
of any size subsets of the eight channels. In addition it allows software to manage the
interrupt reporting for the channel conversion sets.
EXAMPLE
BW_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE);
Address:
2278
Reset
Reset
TEMPSENSE_
DIVIDE_BY_
VTHSENSE
Bit
Bit
W
W
RSRVD3
R
R
31 24
23 16
14 13
TWO
PWD
Field
15
31
15
0
1
HW_LRADC_CTRL2
VTHSENSE
30
14
0
0
Each bit of this eight bit field corresponds to a channel of an LRADC. Setting the bit to one caused the A/D
converter to use its analog divide by two circuit for the conversion of the corresponding channel.
Reserved
Power down the tempsense block.
0x0
0x1
Vth Measurement Control (Channel11)
29
13
0
0
ENABLE — When this is low the tempsense gain block muxes to LRADC channel 8 and 9.
DISABLE — .
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
DIVIDE_BY_TWO
28
12
0
0
HW_LRADC_CTRL2 field descriptions
8005_0000h base + 20h offset = 8005_0020h
27
11
RSRVD2
0
0
26
10
0
0
25
0
0
9
24
0
0
8
Description
23
0
0
7
TEMP_ISRC1
22
0
0
6
21
0
5
0
20
RSRVD3
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
TEMP_ISRC0
18
0
0
2
17
0
0
1
16
0
0
0
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