MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1686

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
26.4.34 ENET MAC Accelerator Receive Function Configuration Register
Address:
1686
Reset
Reset
TX_PROTCHK_
TX_IPCHK_INS
Bit
Bit
W
W
RSRVD0
RSRVD1
SHIFT16
R
R
Field
31 5
INS
2 1
4
3
0
15
31
0
0
HW_ENET_MAC_IPACCRXCONF
800F_01C4h
(HW_ENET_MAC_IPACCRXCONF)
14
30
0
0
Reserved bits. Write as 0.
Enable insertion of protocol checksum. If enabled (1) and an IP frame with a known protocol is transmitted,
the checksum will be inserted automatically into the frame. The checksum field should be all zero.
Other frames are not modified.
The setting is OR'ed with the pin ff_tx_protchk_ins.
Enable insertion of IP header checksum. If enabled (1) and an IP frame is transmitted, its checksum will be
inserted automatically. The IP header checksum field should be all zero.
If a non-IP frame is transmitted the frame will not be modified.
The setting is OR'ed with the pin ff_tx_ipchk_ins.
Reserved bits. Write as 0.
Enable TX FIFO Shift16 function.
Indicates to the transmit data FIFO, that the frame will be written with 2 additional octets before the frame
data. This means the actual Frame starts at bit 16 of the first word written into the FIFO. This function allows
putting the frame payload on a 32-bit boundary in memory as the 14-byte Ethernet header is extended to a
16 byte header.
13
29
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_ENET_MAC_IPACCTXCONF field descriptions
12
28
0
0
11
27
0
0
RSRVD0[15:5]
10
26
0
0
800F_0000h base + 1C4h offset =
25
0
0
9
RSRVD0[31:16]
24
0
0
8
Description
23
0
0
7
22
0
0
6
21
5
0
0
20
4
0
0
Freescale Semiconductor, Inc.
19
0
0
3
18
RSRVD1
0
0
2
17
0
0
1
16
0
0
0