MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1996

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
Address:
1996
Reset
Reset
TXFIFOTHRES
TXSCHEALTH
TXSCHOH
Bit
Bit
W
W
R
R
RSVD2
RSVD1
RSVD0
31 22
21 16
15 13
Field
12 8
6 0
7
31
15
0
0
RSVD1
HW_USBCTRL_TXFILLTUNING 8008_0000h base + 164h offset = 8008_
0164h
30
14
0
0
Reserved.
These bits are reserved and their value has no effect on operation.
FIFO Burst Threshold.
When S/W changes the USBMODE.CM to Host(11), the field defaults to 2.
This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before
the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to
maximize USB performance. A higher value can be used in systems with unpredictable latency and/or
insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO
to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable
bit in USBMODE register is set.
Reserved.
These bits are reserved and their value has no effect on operation.
Scheduler Health Counter.
This register increments when the host controller fails to fill the TX latency FIFO to the level programmed
by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame.
This health counter measures the number of times this occurs to provide feedback to selecting a proper
TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31.
Reserved.
This bit is reserved and its value has no effect on operation.
Scheduler Overhead.
This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an
approximation, the value chosen for this register should limit the number of back-off events captured in the
TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for
this register is not desired as it can needlessly reduce USB utilization.
The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode for
OTG & SPH.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_USBCTRL_TXFILLTUNING field descriptions
28
12
0
0
27
11
0
0
RSVD2
TXSCHEALTH
26
10
0
0
25
0
0
9
24
0
0
8
Description
RSVD0
23
0
0
7
22
0
0
6
21
0
5
0
20
0
4
0
TXSCHOH
Freescale Semiconductor, Inc.
TXFIFOTHRES
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0