MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1947

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
USE_LCR2
TXIFLSEL
RSVD3
CTSEN
RTSEN
RSVD4
18 16
OUT2
OUT1
Field
RTS
DTR
RXE
TXE
LBE
5 3
19
15
14
13
12
11
10
9
8
7
6
0x5
0x6
0x7
Reserved, do not modify, read as zero.
Transmit Interrupt FIFO Level Select. The trigger points for the transmit interrupt are as follows:
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
CTS Hardware Flow Control Enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only
transmitted when the nUARTCTS signal is asserted.
RTS Hardware Flow Control Enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only
requested when there is space in the receive FIFO for it to be received. The FIFO space is controlled by
RXIFLSEL value.
This bit is the complement of the UART Out2 (nUARTOut2) modem status output. This bit is not supported.
This bit is the complement of the UART Out1 (nUARTOut1) modem status output. This bit is not supported.
Request To Send. Software can manually control the nUARTRTS pin through this bit when RTSEN = 0.
This bit is the complement of the UART request to send (nUARTRTS) modem status output. That is, when
the bit is programmed to a 1, the output is 0.
Data Transmit Ready. This bit is the complement of the UART data transmit ready (nUARTDTR) modem
status output. This bit is not supported.
Receive Enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for
the UART signals. When the UART is disabled in the middle of reception, it completes the current character
before stopping.
Transmit Enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs
for the UART signals. When the UART is disabled in the middle of transmission, it completes the current
character before stopping.
Loop Back Enable. This feature reduces the amount of external coupling required during system test. If this
bit is set to 1, the UARTTXD path is fed through to the UARTRXD path. When this bit is set, the modem
outputs are also fed through to the modem inputs.
=If this bit is set to 1, the Line Control 2 Register values are used.
Reserved, do not modify, read as zero.
HW_UARTAPP_CTRL2 field descriptions (continued)
INVALID5 — Reserved.
INVALID6 — Reserved.
INVALID7 — Reserved.
EMPTY — Trigger on FIFO less than or equal to 2 of 16 entries.
ONE_QUARTER — Trigger on FIFO less than or equal to 4 of 16 entries.
ONE_HALF — Trigger on FIFO less than or equal to 8 of 16 entries.
THREE_QUARTERS — Trigger on FIFO less than or equal to 12 of 16 entries.
SEVEN_EIGHTHS — Trigger on FIFO less than or equal to 14 of 16 entries.
INVALID5 — Reserved.
INVALID6 — Reserved.
INVALID7 — Reserved.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Description
Chapter 30 Application UART (AUART)
1947