MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1287

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

completes, one in the GPMI and four in the BCH, are independently stalled as they complete
and try to deliver to the next stage in the data flow. Several of these stages can be skipped
if no-errors are found or once an uncorrectable error is found in a block.
In any case, the final stage will stall if the status register is busy waiting for the CPU to take
status register results. The hardware monitors the state of the
HW_BCH_CTRL_COMPLETE_IRQ bit. If it is still set when the last pipeline stage is
ready to post data, then the stage will stall. It follows that the next previous stage will stall
when it is ready to hand off work to the final stage, and so on up the pipeline.
16.5 Behavior During Reset
A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set
CLKGATE when setting SFTRST. The reset process gates the clocks automatically.
16.6 Programmable Registers
BCH Hardware Register Format Summary
Freescale Semiconductor, Inc.
8000_A000
8000_A010
8000_A020
8000_A030
8000_A040
8000_A050
8000_A070
Absolute
address
(hex)
Hardware BCH ECC Accelerator Control Register
(HW_BCH_CTRL)
Hardware ECC Accelerator Status Register 0
(HW_BCH_STATUS0)
Hardware ECC Accelerator Mode Register (HW_BCH_MODE)
Hardware BCH ECC Loopback Encode Buffer Register
(HW_BCH_ENCODEPTR)
Hardware BCH ECC Loopback Data Buffer Register
(HW_BCH_DATAPTR)
Hardware BCH ECC Loopback Metadata Buffer Register
(HW_BCH_METAPTR)
Hardware ECC Accelerator Layout Select Register
(HW_BCH_LAYOUTSELECT)
It is important that firmware read the STATUS0/1 results and
save them before clearing the interrupt request bit. Otherwise, a
transaction and its results could be completely lost.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Register name
HW_BCH memory map
CAUTION
Chapter 16 20-BIT Correcting ECC Accelerator (BCH)
(in bits)
Width
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R
E4E4_E4E4h
00E0_0000_
Reset value
0000_0010h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000h
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