MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1599

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

26.2.2.1.1.16
written by the uDMA into this BD's data section. If L equals 0, the value written will be
equal to EMRBR. If L equals 1, complete length of the frame including the CRC. It is
written by the uDMA once as the BD is closed.
26.2.2.1.1.17
26.2.2.1.1.18
points to the first location of the associated data buffer, must always be evenly divisible by
16.
26.2.2.1.20 Legacy FEC Transmit Buffer Descriptor
This section discusses the legacy FEC transmit buffer descriptors.
The following sections reference
26.2.2.1.20.1
to indicate the buffer descriptor is ready for transmission. The uDMA clears this bit at the
start of data transmission.
26.2.2.1.20.2
read/write bit will not be modified by hardware, nor will its value affect the hardware.
26.2.2.1.20.3
change from the FEC.
Freescale Semiconductor, Inc.
• 0 The next buffer descriptor is found in the consecutive location.
• 1 The next buffer descriptor is found at the location defined in ETDSR.
Offset + 0
Offset + 2
Offset + 4
Offset + 6
Data Length
Data length. Written by the uDMA. Data length is the number of octets
RX Data Buffer Pointer - A[31:16]
RX data buffer pointer, bits [31:16].
RX Data Buffer Pointer - A[15:0]
RX data buffer pointer, bits [15:0]. The receive buffer pointer, which always
Bit-15 R
Ready. Written by the uDMA (=0) and the user (=1). It is set by the user
Bit-14 TO1
Transmit software ownership. This field is reserved for software use. This
Bit-13 W
Wrap. Written by user. The functionality and operation of this bit does not
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
15
Table 26-2. Legacy FEC Transmit Buffer Descriptor
R
TO1
14
13
W
TO2
12
Table
11
L
26-2.
TC
10
TX Data Buffer Pointer A[31:16]
TX Data buffer Pointer A[15:0]
ABC
9
Data length
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Chapter 26 Ethernet Controller (ENET)
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