MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 429
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
- MCIMX283DVM4B PDF datasheet
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The command register controls the overall operation of each DMA command for this channel.
It includes the number of bytes to transfer to or from the device, the number of APB PIO
command words included with this command structure, whether to interrupt at command
completion, whether to chain an additional command to the end of this one and whether
this transfer is a read or write DMA transfer.
Address:
Freescale Semiconductor, Inc.
Reset
Reset
Bit
Bit
W
W
XFER_COUNT
R
R
CMDWORDS
31 16
15 12
31
15
Field
0
0
HW_APBH_CH7_CMD
CMDWORDS
30
14
0
0
29
13
0
0
This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI3
device. A value of 0 indicates a 64 Kbytes transfer.
This field indicates the number of command words to send to the GPMI3, starting with the base PIO
address of the GPMI3 and increment from there. Zero means transfer NO command words
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_APBH_CH7_CMD field descriptions
27
11
0
0
8000_4000h base + 430h offset = 8000_4430h
RSVD1
26
10
0
0
25
0
0
9
XFER_COUNT
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
24
0
0
8
23
Description
0
0
7
22
0
0
6
21
0
5
0
RSVD0
20
0
4
0
19
0
0
3
18
0
0
2
COMMAND
17
0
0
1
16
0
0
0
429
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