MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1627

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 26 Ethernet Controller (ENET)
26.3.7.6 VLAN Frames Processing
VLAN frames have a Length / Type field set to 0x8100 immediately followed by a 16-Bit
VLAN Control Information field. VLAN tagged frames are received as normal frames
(VLAN Tag not interpreted by the MAC function) and are completely (Including the VLAN
tag) pushed to the user application. If the length/type field of the VLAN tagged frame,
which is found four octets later in the frame is less than 42, padding will be removed. In
addition, the frame status word (Core signal ff_rx_err_stat(7)) indicates that the current
frame is VLAN tagged.
26.3.7.7 Pause Frame Termination
Pause frames are terminated within the receive engine and not transferred to the receive
FIFO. The Quanta is extracted and sent to the MAC Transmit path through a small internal
Clock Rate decoupling asynchronous FIFO.
The Quanta is written only if a correct CRC and a correct frame length are detected by the
control state machine. If not, the Quanta is discarded and the MAC Transmit path is not
paused.
Good Pause Frames are ignored if the register bit FCE is set to '0' and are forwarded to the
Client interface when register bit PAUSE_FWD is set to '1'.
26.3.7.8 CRC Check
The CRC-32 field is checked and is forwarded to the Core FIFO interface if the Core
configuration registers CRC_FWD and PAD_EN are set to '0' and '1' respectively. When
the Core register CRC_FWD is set to '1' (Regardless of PAD_EN register value), the CRC-32
field is checked and terminated (Not transmitted to the Core FIFO).
The CRC polynomial, as specified in the 802.3 Standard, is as follows:
• FCS(X) = X 32 +X 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 +X 8 +X 7 +X 5 +X
4 +X 2 +X 1 +1
The 32 bits of the CRC value are placed in the FCS field so that the X31 term is the
right-most bit of the first octet. The CRC bits are thus received in the following order: X31,
X30,..., X1, X0.
If a CRC error is detected, the frame is marked invalid and ff_rx_err_stat(3) is set °Æ1°Ø.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
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