MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2086

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
2086
Reset
COMBINE_MPU_
BM_ERROR_IRQ
SECOND_FIELD
RECOVER_ON_
UNDERFLOW
BM_ERROR_
INTERLACE_
INTERLACE_
FIFO_CLEAR
ALTERNATE_
WR_STRB
PACKING_
Bit
IRQ_ON_
W
RSRVD1
FORMAT
R
IRQ_EN
START_
FIELDS
FROM_
FIELDS
BYTE_
31 28
19 16
Field
27
26
25
24
23
22
21
20
15
0
14
0
Reserved bits. Write as 0.
If this bit is not set, the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the
LCD_RD_E pin in the 6800 mode. If it is set, the write strobe of both the 6800 and 8080 modes will be driven
only on the LCD_WR_RWn pin. Note that this does not work for read strobe.
This bit is set to enable bus master error interrupt in the LCDIF master mode.
This bit is set to indicate that an interrupt is requested by the LCDIF block. This bit is cleared by software
by writing a one to its SCT clear address. This bit will be set when the LCDIF is in master mode and an error
response was returned by the slave.
0x0
0x1
Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the
current field/frame.
Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field.
It will work only in LCDIF_MASTER is set to 1.
The default is to grab the odd lines first and then the even lines. Set this bit if it is required to grab the even
lines first and then the odd lines. (Line numbers start from 1, so odd lines are 1,3,5,etc. and even lines are
2,4,6, etc.)
Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO.
If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise
it will issue the interrupt on both odd and even field. This bit is mostly relevant if INTERLACE_FIELDS is
set. This feature is only available in DOTCLK and DVI modes.
This bitfield is used to show which data bytes in the 32-bit word written in the HW_LCDIF_DATA register
are valid and should be transmitted. Default value 0xf indicates that all bytes are valid. For 8-bit transfers,
any combination in this bitfield will mean valid data is present in the corresponding bytes. In the 16-bit mode,
a 16-bit half-word is valid only if adjacent bits [1:0] or [3:2] or both are 1. A value of 0x0 will mean that none
of the bytes are valid and should not be used. For example, set the bit field value to 0x7 if the display data
is arranged in the 24-bit unpacked format (A-R-G-B where A value does not have be transmitted). When
input data is is in YCbCr 4:2:2 format (YCBCR422_INPUT is 1), H_COUNT should be the number of pixels
that should be fetched by the block and the BYTE_PACKING_FORMAT should be 0xF.(Note -
YCBCR422_INPUT = 1 implies 2 pixels per 32 bits).
13
0
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
12
0
HW_LCDIF_CTRL1 field descriptions
11
0
10
0
0
9
0
8
Description
0
7
0
6
RSRVD0
5
0
4
0
Freescale Semiconductor, Inc.
0
3
0
2
0
1
0
0