MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1006

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
13.2.4 OTP Key
After a system reset, the OTP controller will read the e-fuse devices and provide the OTP
key information over a private parallel 32-bit interface. While the OTP key is normally not
available to read operations, the module will allow the key to be read if the
otp_crypto_key_ren (read-enable) input is active (high). This allows verification of the key
after it has been programmed in to the e-fuse device. After programming has been validated,
another fuse will be set to disable the read capability.
The OTP key may be selected using the OTP_KEY bit in the control field of the packet
descriptor or by using the key select 0xFF in the CTRL1 field of the descriptor. The DCP
also supports a second hardware key called the UNIQUE_KEY which is generated from
the OTP KEY (OCOTP_CRYPTO0,1,2,3) and key modifier bits from another OTP fields
(OCOTP_OPS2 and OCOTP_UN2) with unique number for every chip. This key is unique
to the device and may be used for encrypting private data stored on the NAND. This key
may be selected by writing 0xFE to the KEY_SELECT field in the CTRL1 packet data.
13.2.5 Managing DCP Channel Arbitration and Performance
The DCP can have four channels all competing for DCP resources to complete their
operations. Depending on the situation, critical operations may need to be prioritized above
less important operations to ensure smooth system operation. To help software achieve this
goal, the DCP implements a programmable arbiter for internal DCP operations and provides
recovery timers on each channel to throttle channel activity.
13.2.5.1 DCP Arbitration
The DCP implements a multi-tiered arbitration policy that allows software a lot of flexibility
in scheduling DCP operations. The following figure illustrates the arbitration levels and
where each channel fits into the arbitration scheme.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1006
Freescale Semiconductor, Inc.