MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1632

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Full Duplex Flow Control Operation
26.3.9.2 Remote Device Congestion
When the MAC Transmit control gets a valid Pause Quanta from the receive path and if
the bit FCE is set to '1', the MAC Transmit logic completes the transfer of the current Frame,
stops sending data for the amount of time specified by the Pause Quanta in 512 bit time
increments and asserts the bit RFC_PAUSE.
Frame transfer resumes when the time specified by the Quanta has expired and if no new
Quanta value has been received or if a new Pause Frame with a Quanta value set to 0x0000
is received. The MAC also resets the bit RFC_PAUSE to '0'.
If the register bit FCE is set to '0', Pause Frames received by the MAC are ignored.
Optionally and independently of the FCE register bit setting, Pause Frame are forwarded
to the Client interface if the register bit PAUSE_FWD is set to '1'.
26.3.9.3 Local Device / FIFO Congestion
Pause Frames are generated by the MAC transmit engine, when the local receive FIFO is
not able to receive more than a pre-defined number of words (FIFO programmable threshold)
or when a Pause Frame generation is requested by the Local Host Processor:
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• Remote Device Congestion: The Remote device connected to the same Ethernet segment
• Core FIFO Congestion: When the Core's receive FIFO reaches a user programmable
• Local Device Congestion: Any device connected to the Core can request (Typically
• To generate a Pause Frame, the Host Processor asserts the register TFC_PAUSE. A
• A XOFF Pause Frame is generated when the Receive FIFO asserts its section empty
• A XON Pause Frame is generated when the Receive FIFO de-asserts its section empty
as the Core reports a Congestion requesting the Core to stop sending Data.
threshold (rx section empty), the Core sends a Pause Frame back to the Remote device
requesting data transfer to be stopped.
through the Host Processor) the remote device to stop transmitting data.
single pause frame is generated when the current Frame transfer is completed and the
register bit TFC_PAUSE is automatically cleared. Optionally, an interrupt () is generated.
flag (internal). A XOFF Pause Frame is generated automatically, when the current
Frame transfer is completed.
flag (internal). A XON Pause Frame is generated automatically, when the current Frame
transfer is completed.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.