MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1672

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
26.4.11 ENET MAC Physical Address Lower Register
Address:
Re-
1672
set
Bit
W
R
RFC_PAUSE
TFC_PAUSE
31
RSRVD0
0
PADDR1
FEDN
Field
Field
31 0
GTS
30
4
3
2
1
0
0
29
0
HW_ENET_MAC_PALR
(HW_ENET_MAC_PALR)
28
0
101: Supplemental MAC Address 1 programmed on SMAC_1_0 and SMAC_1_1 registers is used as the
source address.
110: Supplemental MAC Address 2 programmed on SMAC_2_0 and SMAC_2_1 registers is used as the
source address.
other (any value other than above): Supplemental MAC Address 3 programmed on SMAC_3_0 and
SMAC_3_1 registers is used as the source address.
Receive frame control pause. This read-only status bit is asserted when a full duplex flow control pause
frame is received and the transmitter pauses for the duration defined in this pause frame.This bit automatically
clears when the pause duration is complete.
Transmit frame control pause. Transmits a PAUSE frame when asserted. When this bit is set, the MAC
stops transmission of data frames after the current transmission is complete. At this time, GRA interrupt in
the EIR register is asserted. With transmission of data frames stopped, MAC transmits a MAC Control
PAUSE frame. Next, the MAC clears the TFC_PAUSE bit and resumes transmitting data frames. If the
transmitter pauses due to user assertion of GTS or reception of a PAUSE frame, the MAC may continue
transmitting a MAC Control PAUSE frame.
Full duplex enable. If set, frames transmit independent of carrier sense and collision inputs. This bit should
only be modified when ETHER_EN is cleared.
Reserved bits. Write as 0.
Graceful transmit stop. When this bit is set, MAC stops transmission after any frame currently transmitted
is complete and GRA interrupt in the EIR register is asserted. If frame transmission is not currently underway,
the GRA interrupt will be asserted immediately. Once transmission has completed, a restart can accomplish
by clearing the GTS bit. The next frame in the transmit FIFO is then transmitted. If an early collision occurs
during transmission when GTS equals 1, transmission stops after the collision. The frame is transmitted
again once GTS is cleared. There may be old frames in the transmit FIFO that transmit when GTS is
reasserted. To avoid this, clear the ECR register bit ETHER_EN following the GRA interrupt.
Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used
for exact match and the source address field in PAUSE frames.
27
0
26
0
HW_ENET_MAC_TCR field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
HW_ENET_MAC_PALR field descriptions
23
0
22
0
800F_0000h base + E4h offset = 800F_00E4h
21
0
20
0
19
0
18
0
17
0
PADDR1
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0