MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 158
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MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
- MCIMX283DVM4B PDF datasheet
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Programmable Registers
5.4.11 Interrupt Collector Interrupt Register 1 (HW_ICOLL_INTERRUPT1)
This register provides a mechanism to specify the priority level for an interrupt source. It
also provides an enable and software interrupt for each one, as well as security designation.
HW_ICOLL_INTERRUPT1: 0x130
HW_ICOLL_INTERRUPT1_SET: 0x134
HW_ICOLL_INTERRUPT1_CLR: 0x138
HW_ICOLL_INTERRUPT1_TOG: 0x13C
This register provides a mechanism to specify the priority associated with an interrupt bit.
In addition, this register controls the enable and software generated interrupt. WARNING:
Modifying the priority of an enabled interrupt may result in undefined behavior. You should
always disable an interrupt prior to changing its priority.
EXAMPLE
HW_ICOLL_INTERRUPT1_SET(0,0x00000001);
Address:
158
Reset
PRIORITY
SOFTIRQ
Bit
W
ENABLE
R
Field
1 0
3
2
31
0
HW_ICOLL_INTERRUPT1 8000_0000h base + 130h offset = 8000_0130h
30
0
Set this bit to one to force a software interrupt.
0x0
0x1
Enable the interrupt bit through the collector.
0x0
0x1
Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest).
0x0
0x1
0x2
0x3
HW_ICOLL_INTERRUPT0 field descriptions (continued)
29
0
NO_INTERRUPT — turn off the software interrupt request.
FORCE_INTERRUPT — force a software interrupt
DISABLE — Disable
ENABLE — Enable
LEVEL0 — level 0, lowest or weakest priority
LEVEL1 — level 1
LEVEL2 — level 2
LEVEL3 — level 3, highest or strongest priority
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
0
27
0
26
0
25
0
RSRVD1[31:16]
24
0
Description
23
0
22
0
21
0
20
0
Freescale Semiconductor, Inc.
19
0
18
0
17
0
16
0
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